1. Field of the Invention
The present invention relates to a method and apparatus for generating a variable delay clock and in particular to a system of controlling the delay of a clock with high resolution in the delay.
2. Description of Related Art
DLL (delay lock loop) is well known in prior art for clock generation. FIG. 1 depicts a functional block diagram of a typical N-stage DLL 100, which comprises: a VCDL (voltage-controlled delay line) 110, a PD (phase detector) 120, and a LF (loop filter) 130. VCDL 110 further comprises N variable delay cells 111_1, 111_2, and so on. VCDL 110 receives an input clock CLK_IN and a control voltage Vc from LF 130, and generates N output clocks CLK_1, CLK_2, and so on. CLK_1 is the output of the 1st variable delay cell 111_1, CLK_2 is the output of the 2nd variable delay cell 111_2, and so on. All N delay cells (111_1, 111_2, and so on) are constructed from substantially the same circuit; therefore they all cause substantially the same amount of delay to their respective inputs. The phase of the output clock CLK_N from the last variable delay cell 111_N is compared with the phase of the input clock CLK_IN by the PD 120, which generates a phase error signal PE indicative of the phase relationship between the input clock CLK_IN and the output clock CLK_N. The phase error signal PE generated by PD 120 is filtered by the LF 130, resulting in the control voltage Vc to control the delay for each of the N delay cells of VCDL 110. In steady state, a steady control voltage Vc is established so that the output clock CLK_N is aligned with the input clock CLK_IN; the phase error signal PE is virtually zero, indicating no further change to the control voltage Vc is needed. Let the period of the input clock CLK_IN be T. In steady state, each delay cell (111_1, 111_2, and so on) must cause a delay of TIN so that CLK_N can be aligned with CLK_IN. In many applications, a phase inversion operation (not shown in FIG. 1) is performed at the output of the last delay cell to generate an additional 180-degree phase shift (or equivalent T/2 delay). In this case, each delay cell (111_1, 111_2, and so on) causes a delay of T/(2N) in steady state.
A clock multiplexer is often used along with a DLL to generate a clock of a variable phase (or delay). A clock generation system 200 constructed using a N-stage DLL 100 and a clock multiplexer 220 is illustrated in FIG. 2. N-stage DLL 100 receives an input clock CLK_IN and generates N output clocks CLK_1, CLK_2, and so on, in a manner illustrated in FIG. 1. Clock multiplexer 220 receives those N output clocks from N-stage DLL 100 along with a control signal PHASE_SELECT, and generates CLK_OUT as the output clock of the clock generation system 200. The output clock CLK_OUT is selected among the N output clocks CLK_1, CLK_2, and so on, based on the PHASE_SELECT signal.
Although prior art clock generation system 200 can generate a clock with a desired phase (or delay), there are two problems. First, a clock multiplexer circuit is needed. A high frequency clock multiplexer is hard to implement in an integrated circuits, especially when the number of inputs is high. Second, the resolution of the delay depends on the number of stages of delay buffers. In general, a N-stage DLL (with an aforementioned phase inversion at the output of the last delay cell) provides a resolution of 180/N degrees in phase delay. To achieve a 10-degrees resolution of phase delay, for instance, it takes an 18-stage DLL. Therefore, it is impractical to use DLL to generate a variable delay clock with high resolution in the phase delay.
What is needed is a clock generation system that offers a high resolution in clock phase yet does not require a high complexity phase multiplexer.